A semiconductor lab in your browser. Describe a circuit in plain English and OpenCores generates synthesizable HDL, runs verification, and produces fabrication-ready GDSII.
Trusted by researchers at MIT, Stanford, UC Berkeley, Georgia Tech, Carnegie Mellon, KIT, and TU Delft.
Write a one-line spec or a multi-module brief. OpenCores understands the intent and proposes an architecture.
A fine-tuned model produces Verilog and a self-checking testbench. Six agents verify functional and timing behavior.
One click to OpenLane2 + SKY130 (130nm today, 45nm soon). Download the GDS, view metrics, iterate.
Beta · students only
Coming soon
Coming soon
Paid plans are not open yet. During the closed beta the platform is limited to verified students and academic researchers — request edu credits from inside the app.